TC74HC573AP Description
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Its 8-bit D-type latche is controlled by a latch enable input (LE) and an output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state.
TC74HC573AP Key Features
- High speed: tpd = 13 ns (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
- High noise immunity: VNIH = VNIL = 28% VCC (min)
- Output drive capability: 15 LSTTL loads
- Symmetrical output impedance: |IOH| = IOL = 6 mA (min)
- Balanced propagation delays: tpLH ∼- tpHL
- Wide operating voltage r