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TC74HCT138AP - 3-to-8 Line Decoder

Download the TC74HCT138AP datasheet PDF. This datasheet also covers the TC74HCT138AF variant, as both devices belong to the same 3-to-8 line decoder family and are provided as variant models within a single manufacturer datasheet.

Features

  • High speed: tpd = 17 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • Compatible with TTL outputs: VIH = 2 V (min) VIL = 0.8 V (max).
  • Wide interfacing ability: LSTTL, NMOS, CMOS.
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Pin and function compatible with 74LS138 Pin Assignment TC74HCT138AP T.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HCT138AF_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Toshiba

Part Number Description
TC74HCT138AF 3-to-8 Line Decoder
TC74HCT138AFW 3-TO-8 LINE DECODER
TC74HCT139AF Dual 2-to-4 Line Decoder
TC74HCT139AFW DUAL 2-TO-4 LINE DECODER
TC74HCT139AP Dual 2-to-4 Line Decoder

Full PDF Text Transcription

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TC74HCT138AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT138AP, TC74HCT138AF 3-to-8 Line Decoder The TC74HCT138A is a high speed CMOS 3-to-8 LINE DECODER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high.
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