TC74HCT240AP Overview
They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Their inputs are patible with TTL, NMOS, and CMOS output voltage levels. The TC74HCT240A is an inverting 3-state buffer having two active-low output enables.
TC74HCT240AP Key Features
- High speed: tpd = 13 ns (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
- patible with TTL outputs: VIL = 0.8 V (max)
- VIH = 2.0 V (min)
- Wide interfacing ability: LSTTL, NMOS, CMOS
- Output drive capability: 15 LSTTL loads
- Symmetrical output impedance: |IOH| = IOL = 6 mA (min)
- Balanced propagation delays: tpLH ∼- tpHL
- Wide operating voltage range: VCC (opr) = 2 to 6 V
- Pin and function patible with 74LS240/244