TC74HCT373AP Overview
It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. Their inputs are patible with TTL, NMOS, and CMOS output voltage levels. These 8-bit D-type latches are controlled by a latch enable input (LE) and an output enable input ( OE.
TC74HCT373AP Key Features
- High speed: tpd = 17 ns (typ.) at VCC = 5 V
- Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
- patible with TTL outputs: VIH = 2 V (min)
- Wide interfacing ability: LSTTL, NMOS, CMOS
- Output drive capability: 15 LSTTL loads
- Symmetrical output impedance: |IOH| = IOL = 6 mA (min)
- Balanced propagation delays: tpLH ∼- tpHL
- Pin and function patible with 74LS373