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TC74HCT7007AP - Hex Buffer

Download the TC74HCT7007AP datasheet PDF. This datasheet also covers the TC74HCT7007AF variant, as both devices belong to the same hex buffer family and are provided as variant models within a single manufacturer datasheet.

Features

  • High speed: tpd = 11 ns (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 1 μA (max) at Ta = 25°C.
  • Compatible with TTL outputs: VIH = 2 V (min) VIL = 0.8 V (max).
  • Wide interfacing ability: LSTTL, NMOS, CMOS.
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced propagation delays: tpLH ≈ tpHL.
  • Pin and function compatible with 74LS07 Pin Assignment TC74HCT7007AP TC74HCT70.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74HCT7007AF_ToshibaSemiconductor.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Toshiba

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TC74HCT7007AF Hex Buffer
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Full PDF Text Transcription

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TC74HCT7007AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HCT7007AP, TC74HCT7007AF Hex Buffer The TC74HCT7007A is a high speed CMOS BUFFER fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TTL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. The internal circuit is composed of 4 stages including a buffer output, which provides high noise immunity and stable output. All inputs are equipped with protection circuits against static discharge or transient excess voltage. Features • High speed: tpd = 11 ns (typ.
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