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TC74LVX138FT - 3-to-8 Line Decoder

This page provides the datasheet information for the TC74LVX138FT, a member of the TC74LVX138F 3-to-8 Line Decoder family.

Features

  • High-speed: tpd = 5.5 ns (typ. ) (VCC = 3.3 V).
  • Low power dissipation: ICC = 4 μA (max) (Ta = 25°C).
  • Input voltage level: VIL = 0.8 V (max) (VCC = 3 V) VIH = 2.0 V (min) (VCC = 3 V).
  • Power-down protection provided on all inputs.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Pin and function compatible with 74HC138 TC74LVX138F TC74LVX138FT Weight SOP16-P-300-1.27A TSSOP16-P-0044-0.65A : 0.18 g (typ. ) : 0.06 g (typ. ) Start of commerci.

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Full PDF Text Transcription

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TC74LVX138F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LVX138F, TC74LVX138FT 3-to-8 Line Decoder The TC74LVX138F/ FT is a high-speed CMOS 3-to-8 line decoder fabricated with silicon gate CMOS technology. Designed for use in 3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. This device is suitable for low-voltage and battery operated systems. When the device is enabled, 3 Binary Select inputs (A, B and C) determine which one of the outputs ( Y0 - Y7 ) will go low. When enable input G1 is held low or either G2A or G2B is held high, decoding function is inhibited and all outputs go high. G1, G2A , and G2B inputs are provided to ease cascade connection and for use as an address decoder for memory systems.
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