TC74LVX245FT Datasheet PDF (Octal Bus Transceiver) | Download Toshiba Semiconductor TC74LVX245FT

TC74LVX245FT - Octal Bus Transceiver

This page provides the datasheet information for the TC74LVX245FT, a member of the TC74LVX245F Octal Bus Transceiver family.

Features

(Note).
High-speed: tpd = 4.7 ns (typ. ) (VCC = 3.3 V).
Low power dissipation: ICC = 4 μA (max) (Ta = 25°C).
Input voltage level: VIL = 0.8 V (max) (VCC = 3 V) VIH = 2.0 V (min) (VCC = 3 V).
Balanced propagation delays: tpLH ∼.
tpHL.
Low noise: VOLP = 0.8 V (max).
Pin and function compatible with 74HC245 TC74LVX245F TC74LVX245FT Weight SOP20-P-300-1.27A TSSOP20-P-0044-0.65A : 0.22 g (typ. ) : 0.08 g (typ. ) Note: Do not apply a signa.

Datasheet Details

Part number	TC74LVX245FT
Manufacturer	Toshiba Semiconductor
File Size	201.59 KB
Description	Octal Bus Transceiver
Datasheet	TC74LVX245FT Datasheet
Additional preview pages of the TC74LVX245FT datasheet.

📁 Similar Datasheet

TC74LCX125FK - Low-Voltage Quad Bus Buffer (Toshiba)

TC74LCX126F - Low-Voltage Quad Bus Buffer (Toshiba)

TC74LCX126FK - Low-Voltage Quad Bus Buffer (Toshiba)

TC74LCX16245FT - Low-Voltage 16-Bit Bus Transceiver (Toshiba)

TC74LCX16373FT - Low-Voltage 16-Bit D-Type Latch (Toshiba)

TC74LCX16374FT - Low-Voltage 16-Bit D-Type Flip-Flop (Toshiba)

TC74LCXZ240FK - Low Voltage Octal Bus Buffer (Toshiba)

TC74LCXZ240FT - Low Voltage Octal Bus Buffer (Toshiba)

TC74LCXZ244FK - Low Voltage Octal Bus Buffer (Toshiba)

TC74LCXZ244FT - Low Voltage Octal Bus Buffer (Toshiba)

Full PDF Text Transcription

Click to expand full text

TC74LVX245F/FT TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74LVX245F, TC74LVX245FT Octal Bus Transceiver The TC74LVX245F/ FT is a high-speed CMOS octal bus transceiver fabricated using silicon gate CMOS technology. Designed for use in 3-V systems, it achieves high-speed operation while maintaining the CMOS low power dissipation. These devices are suitable for low-voltage and battery operated systems. It is intended for two-way asynchronous communication between data busses. The direction of data transmission is determined by the level of the DIR input. The enable input ( G ) can be used to disable the device so that the busses are effectively isolated. All inputs are equipped with protection circuits against static discharge. Features (Note) • High-speed: tpd = 4.

Published: Jul 7, 2006 |