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74HC237D - 3-to-8 Line Decoder/Latch

General Description

2.

The 74HC237D is a high speed CMOS 3-to-8 DECODER ADDRESS LATCH fabricated with silicon gate C2MOS technology.

It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation.

Key Features

  • (1) High speed: tpd = 12 ns (typ. ) at VCC = 5 V (2) Low power dissipation: ICC = 4.0 µA (max) at Ta = 25  (3) Balanced propagation delays: tPLH ≈ tPHL (4) Wide operating voltage range: VCC(opr) = 2.0 V to 6.0 V 4. Packaging SOIC16 ©2016 Toshiba Corporation 1 Start of commercial production 2016-05 2016-08-04 Rev.3.0 5. Pin Assignment 6. Marking 7. IEC Logic Symbol 74HC237D ©2016 Toshiba Corporation 2 2016-08-04 Rev.3.0 8. Truth Table X: Don't care 9. Logic Diagram 74HC237D ©2016 Tosh.

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Datasheet Details

Part number 74HC237D
Manufacturer Toshiba
File Size 223.66 KB
Description 3-to-8 Line Decoder/Latch
Datasheet download datasheet 74HC237D Datasheet

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Full PDF Text Transcription (Reference)

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CMOS Digital Integrated Circuits Silicon Monolithic 74HC237D 74HC237D 1. Functional Description • 3-to-8 Line Decoder/Latch 2. General The 74HC237D is a high speed CMOS 3-to-8 DECODER ADDRESS LATCH fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. It is composed of a 3-bit input latches with a common GL enable input and 3-to-8 line decoder with enable inputs G1 and G2. The 3-bit binary data is stored into the input latch on the high level of GL. The value of this data determines which one of the outputs will go low. When the enable input G1 is held low or G2 is held high, decoding function is inhibited and all the 8 outputs go high.