DF2S14P2CTC
Features
(1) Suitable for use with a 12 V signal line. (VRWM ≤ 12.6 V) (2) Protects devices with its high ESD performance.
(VESD = ±30 k V (Contact / Air) @IEC61000-4-2) (3) Low dynamic resistance protects semiconductor devices from static electricity and noise.
(RDYN = 0.08 Ω (typ.)) (4) Snapback characteristics realizing low clamping voltage protects semiconductor devices.
(VC = 28 V@IPP = 50 A (typ.)) (5) pact package is suitable for use in high density board layouts such as in mobile devices.
(1.6 mm × 0.8 mm size (Nickname: CST2C))
4. Packaging
CST2C
©2017-2018 Toshiba Electronic Devices & Storage Corporation
Start of mercial production
2017-07
2018-12-06 Rev.3.0
5. Example of Circuit Diagram
6. Quick Reference Data
Characteristics
Symbol Note
Test Condition
Min Typ. Max Unit
Working peak reverse voltage
Dynamic resistance
Electrostatic discharge voltage (IEC61000-4-2) (Contact)
VRWM RDYN VESD
(Note 1) (Note 2) (Note 3)
12.6 V
0.08...
