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TC551001APL-70 - SILICON GATE CMOS STATIC RAM

Description

The TC551 001APL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated from a single 5V power supply.

Features

  • with an operating Current of 5mNMHz (typ. ) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low power standby mode in which the standby current is 2~ typically. The TC551 001 APL has three control inputs. Chip enable inputs (CE1, CE2) allow for device selection and data retention control, while an output enable input (OE) provides fast memory access. The TC551 001 APL is suitable for use in microprocessor systems where high speed, low power,.

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Note: The manufacturer provides a single datasheet file (TC551001APL-70-Toshiba.pdf) that lists specifications for multiple related part numbers.

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Full PDF Text Transcription

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TOSHIBA SILICON GATE CMOS 1nC55100lAPL/PUFL/P.U![L/l1]{L-70/85/10OL1) 131,072 WORD x 8 BIT STATIC RAM Description The TC551 001APL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated from a single 5V power supply. Advanced circuit techniques provide both high speed and low power features with an operating Current of 5mNMHz (typ.) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low power standby mode in which the standby current is 2~ typically. The TC551 001 APL has three control inputs. Chip enable inputs (CE1, CE2) allow for device selection and data retention control, while an output enable input (OE) provides fast memory access.
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