Description
The TC551 001 BPL is a 1,048,576 bit CMOS static random access memory organized as 131,072 words by 8 bits and operated from a single 5V power supply.
Features
- with an operating current of 5mNMHz (typ. ) and a minimum cycle time of 70ns. When CE1 is a logical high, or CE2 is low, the device is placed in a low power standby mode in which the standby current is 2jJA typically. The TC551 001 BPL has three control inputs. Chip enable inputs (CE1, CE2) allow for device selection and data retention control, while an output enable input (OE) provides fast memory access. The TC551 001 BPL is suitable for use in microprocessor systems where high speed, low power.