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TC74ACT299F - 8-Bit PIPO Shift Register

Download the TC74ACT299F datasheet PDF. This datasheet also covers the TC74ACT299P variant, as both devices belong to the same 8-bit pipo shift register family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • (Note 1)(Note 2).
  • High speed: fmax = 130 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 8 μA (max) at Ta = 25°C.
  • Compatible with TTL outputs: VIL = 0.8 V (max) VIH = 2.0 V (min).
  • Symmetrical output impedance: |IOH| = IOL = 24 mA (min) Capability of driving 50 Ω transmission lines.
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Pin and function compatible with 74F299 Weight DIP20-P-300-2.54A SOP20-P-300-1.27A : 1.30 g (typ. ) : 0.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (TC74ACT299P-Toshiba.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Toshiba

Part Number Description
TC74ACT299P 8-Bit PIPO Shift Register
TC74ACT257F 2-Channel Multiplexer
TC74ACT257P 2-Channel Multiplexer
TC74ACT280F 9-Bit Parity Generator/Checker
TC74ACT280P 9-Bit Parity Generator/Checker

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74ACT299P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74ACT299P, TC74ACT299F 8-Bit PIPO Shift Register with Asynchronous Clear The TC74ACT299 is an advanced high speed CMOS 8-BIT PIPO SHIFT REGISTER fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. This device may be used as a level converter for interfacing TLL or NMOS to High Speed CMOS. The inputs are compatible with TTL, NMOS and CMOS output voltage levels. It has a four modes (HOLD, SHIFT LEFT, SHIFT RIGHT and LOAD DATA) controlled by the two selection inputs (S0, S1).