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TC74HC40102AP Datasheet Dual Bcd Programmable Down Counter

Manufacturer: Toshiba

Overview: TC74HC40102,40103AP/AF TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74HC40102AP, TC74HC40102AF TC74HC40103AP, TC74HC40103AF TC74HC40102AP/AF Dual BCD Programmable Down Counter TC74HC40103AP/AF 8-Bit Binary Programmable Down Counter The TC74HC40102A and TC74HC40103A are high speed CMOS PROGRAMMABLE DOWN COUNTERS fabricated with silicon gate C2MOS technology. They achieve the high speed operation similar to equivalent LSTTL while maintaining the CMOS low power dissipation. The output terminal ( CO/ZD ) goes to an active low state when the down count reaches zero. Since the TC74HC40102A is designed as a BCD counter, programming up to 99 counts is possible. The TC74HC40103A, with its 8-bit binary construction, can be set to provide up to 255 counts. Both devices have Inhibit Clock ( CI/CE ), Asynchronous Preset Control ( APE ), Synchronous Preset ( SPE ) and Clear Control ( CLR ) inputs for setting the counter to the maximum counting mode. All inputs are equipped with protection circuits against static discharge or transient excess voltage.

General Description

Count Inhibit Count is inhibited regardless of other inputs.

Regular Count Down count on the rising edge of C

Key Features

  • High speed: fmax 40 MHz (typ. ) at VCC = 5 V.
  • Low power dissipation: ICC = 4 μA (max) at Ta = 25°C.
  • High noise immunity: VNIH = VNIL = 28% VCC (min).
  • Output drive capability: 10 LSTTL loads.
  • Symmetrical output impedance: |IOH| = IOL = 4 mA (min).
  • Balanced propagation delays: tpLH ∼.
  • tpHL.
  • Wide operating voltage range: VCC (opr) = 2 to 6 V.
  • Pin and function compatible with 40102B, 40103B Weight DIP16-P-300-2.54A SOP1.

More Datasheets from Toshiba

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TC74HC40102AP Distributor