Datasheet4U Logo Datasheet4U.com

TC74VCX373FT - Low-Voltage Octal D-Type Latch

Key Features

  • Low voltage operation: VCC = 1.2 to 3.6 V.
  • High speed operation: tpd = 4.2 ns (max) (VCC = 3.0 to 3.6 V) tpd = 4.7 ns (max) (VCC = 2.3 to 2.7 V) tpd = 9.4 ns (max) (VCC = 1.65 to 1.95 V) tpd = 18.8 ns (max) (VCC = 1.4 to 1.6 V) tpd = 47.0 ns (max) (VCC = 1.2 V).
  • 3.6 V tolerant inputs and outputs.
  • Output current: IOH/IOL = ±24 mA (min) (VCC = 3.0 V) IOH/IOL = ±18 mA (min) (VCC = 2.3 V) IOH/IOL = ±6 mA (min) (VCC = 1.65 V) IOH/IOL = ±2 mA (min) (VCC = 1.4 V).

📥 Download Datasheet

Datasheet Details

Part number TC74VCX373FT
Manufacturer Toshiba
File Size 285.69 KB
Description Low-Voltage Octal D-Type Latch
Datasheet download datasheet TC74VCX373FT Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
TC74VCX2125FK Low-Voltage Quad Bus Buffer Toshiba Semiconductor
TC74VCX2573FK Low-Voltage Octal D-Type Latch Toshiba Semiconductor
TC74VCX2573FT Low-Voltage Octal D-Type Latch Toshiba Semiconductor
TC74VHC03F Quad 2-Input NAND Gate Toshiba Semiconductor
TC74VHC03FK Quad 2-Input NAND Gate Toshiba Semiconductor

Other Datasheets by Toshiba

Part Number Description
TC74VCX373FK Low-Voltage Octal D-Type Latch
TC74VCX374FK Low-Voltage Octal D-Type Flip-Flop
TC74VCX374FT Low-Voltage Octal D-Type Flip-Flop
TC74VCX374FTG Low-Voltage Octal D-Type Flip-Flop
TC74VCX32FK Low-Voltage Quad 2-Input OR Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
TC74VCX373FT/FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74VCX373FT, TC74VCX373FK Low-Voltage Octal D-Type Latch with 3.6 V Tolerant Inputs and Outputs The TC74VCX373 is a high performance CMOS octal D-type latch which is guaranteed to operate from 1.2-V to 3.6-V. Designed for use in 1.5 V, 1.8 V, 2.5 V or 3.3 V systems, it achieves high speed operation while maintaining the CMOS low power dissipation. It is also designed with over voltage tolerant inputs and outputs up to 3.6 V. The 8 bit D-type latch is controlled by a latch enable input (LE) and an output enable input ( OE ). When the OE input is high, the eight outputs are in a high impedance state. All inputs are equipped with protection circuits against static discharge. Features • Low voltage operation: VCC = 1.