TC74VHCT32AFN Overview
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS low power dissipation. The internal circuit is posed of 4 stages including buffer output, which provide high noise immunity and stable output. The input voltage are patible with TTL output voltage.
TC74VHCT32AFN Key Features
- High speed: tpd = 3.8 ns (typ.) at VCC = 5 V
- Low power dissipation: ICC = 2 μA (max) at Ta = 25°C
- patible with TTL inputs: VIL = 0.8 V (max)
- Power down protection is provided on all inputs and outputs
- Balanced propagation delays: tpLH ∼- tpHL
- Low noise: VOLP = 0.8 V (max)
- Pin and function patible with the 74 series