TXC-05810B Datasheet | Transwitch

.. Cell Bus Access Processor TXC-05810B DATA SHEET Features - - - - - - - - - 155 Mbit/s bidirectional throughput RISC-based hardware architecture Dual independent Cell Bus interfaces for increased bandwidth or redundancy UTOPIA Level 2P interface for cell and packet transport 64-bit synchronous SRAM port for data storage Utilizes ASPEN ATM Access EDGE firmware for design and field upgrades Cell insertion/extraction through host interface Message-based interface for host-ASPEN munication Interoperable with ASPEN-PX (TXC-05811) enabling ASPEN to address up to 64 UTOPIA Level 2 ports ASPEN Device DESCRIPTION The ASPEN device (TXC-05810B) is a revolutionary, RISC-based processor designed to support the requirements of next generation multi-service access systems. The ASPEN supports Cell Bus operation in both cell and packet modes via two independent Cell Bus ports. The ASPEN and Cell Bus may be configured to support redundant system operation or, alternatively, to provide greater system throughput. Line interface is via UTOPIA Level 2 for ATM cells or Level 2P for variable length packets. Buffering of data traffic and control information, such as connection tables, is stored in an external synchronous SRAM. munication to a local host, is message based and via an external Dual Port RAM. The flexible nature of the ASPEN device architecture supports a variety of cell, packet, and cell/packet interworking modes. The ASPEN device’s mode of operation is determined by firmware downloaded into the device instruction memory. Contact Tran Switch for details of UTOPIA Level 2P interface specifications and information on available operational firmware. PRELIMINARY information documents contain information on products in the sampling, pre-production or early production phases of the product life cycle. Characteristic data and other specifications are subject to change. Contact Tran Switch Applications Engineering for current information on this product. - -...