TQ6124 Datasheet | TriQuint Semiconductor

Features Figure 1. TQ6124 Block Diagram - 1Gs/s aggregate bandwidth LSBs CLK NCLK D0 D1 D2 D3 D4 D5 D6 Intermediate Bits D7 D8 D9 MSBs D10 D11 D12 D13 - 14-bit resolution - RF front end - ECL-patible inputs Master Latch - 0.026% DC differential non-linearity - 0.035% DC integral non-linearity MIXED SIGNAL PRODUCTS Delay Stages S1 S2 ... ... ... S14 S15 Segment Encoders - SFDR: 52 d Bc @ FOUT = 75 MHz 48 d Bc @ FOUT = 148 MHz 45 d Bc @ FOUT = 199 MHz - 1.4 W power dissipation - 44-pin ceramic QFP package or die only Slave Latch Current Switches Applications - Direct Digital Synthesis - Pixel generation for workstations and high-end monitors 50 ohm R-2R Ladder Network VO VAA MID_trim LSB_trim VREF VSENSE NVO - Direct-generation of broadband video for cable TV - High-speed arbitrary waveform generators Current Source Array For additional information and latest specifications, see our website: .triquint. Functional Description The TQ6124 registers ining bits in a master latch array. The value of the four most-significant bits is encoded into an n-of-15 thermometer code while the ten low-order bits pass though an equalizing delay stage. All 25 bits are re-registered in a 25-wide slave latch array which drives a set of 25 differential pair switches. These switches steer the corresponding segment and bit currents into the true (VO) and plementary (NVO) outputs. This architecture minimizes glitch impulses by eliminating large mid-scale current transitions. The most-significant bits generate the segment currents, which are of equal weight at 1/16 of the fullscale output (IFS). The ten lower-order bits are divided into two subgroups. The three intermediate bits steer binary-weighted currents of magnitude IFS/32, IFS/64 and IFS/128 to the outputs. The seven least-significant bits steer identical IFS/128 currents into a differential R-2R ladder to generate effective bit currents of IFS/256 to IFS/16384. The DAC output is the sum of the outputs of...