TQ6124 Description
The TQ6124 registers ining bits in a master latch array. The value of the four most-significant bits is encoded into an n-of-15 thermometer code while the ten low-order bits pass though an equalizing delay stage. All 25 bits are re-registered in a 25-wide slave latch array which drives a set of 25 differential pair switches.
TQ6124 Key Features
- 1Gs/s aggregate bandwidth
- 14-bit resolution
- RF front end
- ECL-patible inputs
- 0.026% DC differential non-linearity
- 0.035% DC integral non-linearity
- S14 S15
- SFDR: 52 dBc @ FOUT = 75 MHz 48 dBc @ FOUT = 148 MHz 45 dBc @ FOUT = 199 MHz
- 1.4 W power dissipation
- 44-pin ceramic QFP package or die only