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TA7S20 - Triscend A7S Configurable System-on-Chip Platform

This page provides the datasheet information for the TA7S20, a member of the TA7S04 Triscend A7S Configurable System-on-Chip Platform family.

Datasheet Summary

Description

!

Popular, industry-standard 32bit RISC processor Binary and source code compatible with other ARM7/ARM7TDMI variants Widespread C/C++ compiler, source-level debugger, and RTOS support Superior code density usin

Features

  • , and hold timing. The CPU connects directly to external memory, eliminating any potential latency incurred by using the CSI bus. For low frequency or minimal.

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Datasheet preview – TA7S20

Datasheet Details

Part number TA7S20
Manufacturer Triscend
File Size 1.56 MB
Description Triscend A7S Configurable System-on-Chip Platform
Datasheet download datasheet TA7S20 Datasheet
Additional preview pages of the TA7S20 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com Triscend A7S Configurable System-on-Chip Platform ® August, 2002 (Version 1.10) ! Industry’s first complete 32-bit Configurable System-on-Chip (CSoC) • High-performance, low-power consumption, 32-bit RISC processor (ARM7TDMI™) • 8Kbyte mixed instruction/data cache • 16Kbyte internal scratchpad RAM • Next-generation embedded programmable logic architecture (up to 25,600 ASIC gates) • High-performance dedicated internal bus (up to 455Mbytes per second at 60 MHz) • External memory interface supporting Flash, EEPROM, SRAM, and SDRAM • Advanced real-time, in-system debugging capability • Stand-alone operation from a single external memory (code + initialization) • 2.5-volt core with 3.3- or 2.
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