Unisonic Technologies U74AHC1G74
U74AHC1G74 is a single positive-edge-triggered D-type flip-flop. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse.| Part No. | U74AHC1G74 |
|---|---|
| Datasheet | U74AHC1G74 Download |
| Manufacturer |  Unisonic Technologies |
| Description | SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP |
| Buy | Stock & Price |
DESCRIPTION
The UTC A low level at the preset ( PRE ) or clear ( CLR ) inputs sets or resets the outputs, regardless of the levels of the other inputs. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,data at the D input can be changed without affecting the levels at the outputs.●
FEATURES
* Operation voltage range: 2 ~ 5.5V * Max tPD of 7.3 ns at 5 V * Low static power consumption; ICC=2μA (Max.) * ±8mA output drive at 5 V● ORDERING INFORMATION Ordering Number Lead Free Halogen Free U74AHC1G74L-S08-R U74AHC1G74G-S08-R U74AHC1G74L-SM2-R U74AHC1G74G-SM2-R U74AHC1G74L-CK08-2030-R U74AHC1G74G-CK08-2030-R 1 CDFN2030-8 Package SOP-8 MSOP-8 CDFN2030-8 Packing Tape Reel Tape Reel Tape Reel Copyright © 2023 Unisonic Technologies Co., Ltd 1 of 6 QW-R126-027.B U74AHC1G74
● MARKING SOP-8 / MSOP-8
● PIN CONFIGURATION CDFN2030-8 CMOS IC
● FUNCTION TABLE (each gate) INPUTS OUTPUTS PRE CLR CLK L H X H L X L...
