DESCRIPTION
The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level. The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level. When OVD or UVD detect the fault voltage level, the FPL_N is latched HIGH and PGO goes LOW. The latch can be reset by PDON_N going HIGH. There is 2.4ms delay time for PDON_N turning off FPL_N. When OVD and UVD detect the right voltage level, the power good output (PGO) will be issue. CMOS IC SOP-8 DIP-8 FEATURES
* The Over Voltage Detector (OVD) monitors 3.3V, 5V, 12V input voltage level. * The Under Voltage Detector (UVD) monitors 3.3V, 5V input voltage level. * Both of the power good output (PGO) and the fault protection latch (FPL_N) are Open Drain Output. * 75 ms time delay for UVD. * 300 ms time delay for PGO. * 38 ms for PDON_N input signal De-bounce. * 73 us for internal signal De-glitches. * 2.4 ms time delay for PDON_N turn-off FPL_N. PIN CONFIGURATION PGI GND FPL_N PDON_N 1 2 3 4 8 7 6 5 PGO VDD V5 V33 UTC UNISONIC TECHNOLOGIES CO., LTD.
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