UM83C002
Features
- 3 DMA channels
- Host processor port
- Refresh circuit for dynamic RAM built-in
- RAM access priority network
- Address multiplexing for dynamic RAM
- Multiplexed address and data lines from processor
- Pins arranged for easy integration into 8088/8086 systems
- No lost RAM cycles for DMA break-in
- DMA carry output permits DMA across 64K boun daries
- 24 bit timer or baud rate generator
- T T L patible inputs and outputs. Outputs drive
8 L S T T L loads
General Description
The RAM B U F F E R C O N T R O LLE R contains three high-speed DMA channels: a host puter address port, dynamic RAM refresh circuitry, and RAM access priority logic. One of the DMA address counters points inside the buffer RAM for transferring data between the RAM and the disk. A refresh address counter handles dynamic RAM refreshing. Also on chip is an address multiplexer. The DISK C O N T R O LLE R UM83C001 connects to one of the RAM controller chip's DMA channels. The two other DMA channels may be...
