Datasheet4U Logo Datasheet4U.com

UTCTL074 - LOW NOISE QUAD J-FET OPERATIONAL AMPLIFIER

Datasheet Summary

Description

The UTC TL074 is a high speed J-FET input quad operational amplifier.

It incorporates well matched, high voltage J-FET and bipolar transistors in a monolithic integrated circuit.

Features

  • high slew rates, low input bias and offset current, and low offset voltage temperature coefficient. SOP-14.

📥 Download Datasheet

Datasheet preview – UTCTL074

Datasheet Details

Part number UTCTL074
Manufacturer Unisonic Technologies
File Size 391.11 KB
Description LOW NOISE QUAD J-FET OPERATIONAL AMPLIFIER
Datasheet download datasheet UTCTL074 Datasheet
Additional preview pages of the UTCTL074 datasheet.

📁 Similar Datasheet

  • UTC-1005 - Thin Film Cascadable Amplifier (Teledyne)
  • UTC-1044 - Thin Film Cascadable AMplifier (Agilent Technologies)
  • UTC-111 - Thin-Film Cascadable Amplifier (Teledyne)
  • UTC-2012 - Thin-Film Cascadable Amplifier (Teledyne Cougar)
  • UTC-2321 - Thin-Film Cascadable Amplifier (Teledyne)
  • UTC-3216-421N - Gas Discharge Tube (Unictron)
  • UTC-546 - Thin-Film Cascadable Amplifier (teledyne cougar)
  • UTC1005 - Thin Film Cascadable Amplifier (Teledyne)
  • UTC1018 - FM IF SYSTEM (YOUWANG)
  • UTC1031 - TV Vertical Deflection System (Hangzhou Silan Microelectronics)
Other Datasheets by Unisonic Technologies

Full PDF Text Transcription

Click to expand full text
UTC TL074 LINEAR INTEGRATED CIRCUIT LOW NOISE QUAD J-FET OPERATIONAL AMPLIFIER DESCRIPTION The UTC TL074 is a high speed J-FET input quad operational amplifier. It incorporates well matched, high voltage J-FET and bipolar transistors in a monolithic integrated circuit. The device features high slew rates, low input bias and offset current, and low offset voltage temperature coefficient. SOP-14 FEATURES *Low power consumption *Wide common-mode (up to vcc+ ) and differential voltage range *Low input bias and offset current *Low noise en = 15nV / √ Hz(typ) *Output short-circuit protection *High input impedance J-FET input stage *Low harmonic distortion:0.
Published: |