UT6264B Datasheet | Utron

FEATURES - - 8K X 8 BIT LOW POWER CMOS SRAM The UT6264B is a 65,536-bit low power CMOS static random access memory organized as 8,192 words by 8 bits. It is fabricated using high performance, high reliability CMOS technology. The UT6264B is designed for high-speed and low power application. It is particularly well suited for battery back-up nonvolatile memory application. The UT6264B operates from a single 5V power supply and all inputs and outputs are fully TTL patible. - - - - - - Access time : 35/70ns (max.) Low power consumption: Operating : 60/40 m A (typical) Standby :0.3 m A (typical) normal 2 µA (typical) L-version 1 µA (typical) LL-version Single 5V power supply All inputs and outputs TTL patible Fully static operation Three state outputs Data retention voltage : 2V (min.) Package : 28-pin 600 mil PDIP 28-pin 330 mil SOP FUNCTIONAL BLOCK DIAGRAM A4 A3 A12 A7 A6 A5 A8 A2 ROW DECODER PIN CONFIGURATION . . . MEMORY ARRAY 256 ROWS × 256 COLUMNS VCC VSS I/O1 I/O8 CE . . . . . . I/O CONTROL . . . LOGIC CONTROL PIN DESCRIPTION SYMBOL A0 - A12 I/O1 - I/O8 CE w w w A10 A9 t a .D . . . COLUMN I/O COLUMN DECODER S a e h U 4 t e NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O1 I/O2 I/O3 Vss .c 28 27 26 25 24 23 22 21 20 19 18 17 16 15 m o Vcc NC A8 A9...