VT83201 Datasheet | Vaishali Semiconductor

Description The Vaishali VT83201 is a single-chip, integrated VCXO and Phase Locked Loop (PLL) clock synthesizer. The device uses the VCXO and an analog Phase-Locked Loop (PLL) to accept a 10 MHz to 20 MHz, 30p F (pull range of 200 ppm) crystal input, in order to produce either one or two output clocks. A 0 to 3V control signal is used to fine tune the output clock frequency in the ±100ppm range. Select inputs S0 and S1 are used for frequency and output selection. Features - = - = - = - = - = 3.3V supply operation Packaged in 16-pin SOIC package Replaces separate VCXO and multiplier Uses inexpensive pullable crystal On-chip VCXO with 200 ppm pull range (±100 ppm) - = - = 5V-tolerant control inputs Zero ppm synthesis error in both clocks Figure 1. Functional Block Diagram VDD1 VDD2 VIN X2 Load Cap Control Output Buffer osc Load Caps Low Phase Noise PLL Output Buffer X1 S1:S0 OE CLK2 CLK1 10-20 MHz Pullable Crystal 2001-04-12 Vaishali Semiconductor Page 1 .vaishali. 747 Camden Avenue, Suite C Campbell CA 95008 MDST-0011-01 Ph. 408.377.6060 Fax 408.377.6063 Figure 2. Pin Configuration VT83201 16 pin SOIC X1 VDD1 VDD1 VIN GND GND GND OE 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 NC S1 GND CLK2 VDD2 S0 CLK1 Table 1. Pin Description Name X1 VDD1 VIN GND OE CLK1 S0 VDD2 CLK2 S1 NC X2 1 2,3 4 5,6, 7,13 8 9 10 11 12 14 15 16 Pin # Type XI P I P I O I P O I XO Core VDD. Connect to 3.3V Description Crystal connection. Connect to a pullable crystal of 10- 20 MHz Voltage input to VCXO. Zero to 3V signal controls the frequency of the VCXO. Connect to ground. Active HIGH Output enable . Outputs in Hi-Z state when LOW Clock output #1 per Table 2. Select input #0. Selects output per Table 2 Output VDD. Connect to 3.3V Clock output #2 per Table 2 Select input #1. Selects outputs per Table 2 There is no internal connection to this pin. Crystal connection. Connect to a pullable crystal of 10 MHz - 20 MHz. Legend: I = Input O = Output P = Power supply connection XI,...