Description
The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively.
Features
- Single 3.3V ( ± 0.3V ) power supply.
- High speed clock cycle time : 8/10 for LVTTL.
- High speed clock cycle time : 8/10 for SSTL - 3.
- Fully synchronous with all signals referenced to a positive clock edge.
- Programmable CAS Iatency (2,3).
- Programmable burst length (1,2,4,8,& Full page).
- Programmable wrap sequence (Sequential/Interleave).
- Automatic precharge and controlled precharge.
- Auto refresh and self refresh modes.
VG3664321412BT Datasheet
