VG3664321412BT
Description
Preliminary VG3664321(4)1(2)BT CMOS Synchronous Dynamic RAM The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Key Features
- Single 3.3V ( ± 0.3V ) power supply
- High speed clock cycle time : 8/10 for LVTTL
- High speed clock cycle time : 8/10 for SSTL - 3
- Fully synchronous with all signals referenced to a positive clock edge
- Programmable CAS Iatency (2,3)
- Programmable burst length (1,2,4,8,& Full page)
- Programmable wrap sequence (Sequential/Interleave)
- Automatic precharge and controlled precharge
- Auto refresh and self refresh modes
- Dual Internal banks controlled by A11 (Bank select) for VG36643211(2)
