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Description
Preliminary
VG3664321(4)1(2)BT CMOS Synchronous Dynamic RAM
The device is CMOS Synchronous Dynamic RAM organized as 524,288 - word x 32 - bit x 4 bank, and 1,048,576 - word x 32 - bit x 2 - bank, respectively. lt is fabricated with an advanced submicron CMOS technology and designed to operate from a singly 3.3V only power supply. It is packaged in JEDEC standard pinout and standard plastic TSOP package.
Features
• Single 3.3V ( ± 0.