VG36648041DT Overview
4 (word x bit x bank), respectively. All input and outputs are synchronized with the positive edge of the clock.The synchronous DRAMs are patible with Low Voltage TTL (LVTTL).These products are packaged in 54-pin TSOPII.
VG36648041DT Key Features
- Single 3.3V ( ± 0.3V ) power supply
- Fully synchronous operation referenced to clock rising edge
- Possible to assert random column access in every cycle
- Quad internal banks controlled by A12 & A13 (Bank Select)
- Byte control by LDQM and UDQM for VG36641641D
- Programmable Wrap sequence (Sequential / Interleave)
- Programmable burst length (1, 2, 4, 8 and full page)
- Programmable /CAS latency (2 and 3)
- Automatic precharge and controlled precharge
- CBR (Auto) refresh and self refresh