Description
The device CMOS Dynamic RAM organized as 4,194,304 words x 4 bits with extended data out access mode.
It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 5V only or 3.3V oniy power supply.
Features
- Single 5V( ± 10 %) or 3.3V(3.15V~3.6V) only power supply.
- High speed tRAC access time: 50/60ns.
- Extended - data - out(EDO) page mode access.
- I/O level: TTL compatible (Vcc = 5V) LVTTL compatible (Vcc = 3.3V).
- 4 refresh modes: - RAS only refresh - CAS - before - RAS refresh - Hidden refresh - Self-refresh.
- Refresh interval: - Self-refresh: 2048 cycles.
- JEDEC standard pinout: 26/24-pin plastic SOJ and TSOPII. DataSheet4U. com
DataShe.