SI4736DY Datasheet | Vishay

attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a mercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71012 S-51870⎯Rev. B, 12-Sep-05 .vishay. 1 SPICE Device Model Si4736DY Vishay Siliconix .. SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data Measured Data Unit VGS(th) ID(on) r DS(on) gfs VSD VDS = VGS, ID = 250 μA VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 13 A VGS = 4.5 V, ID = 12 A 1.1 596 0.0079 0.0090 62 0.76 0.61 0.0070 0.0083 56 0.495 0.43 V A Ω S V Drain-Source On-State Resistancea Forward Transconductancea Schottky Diode Forward Voltagea VDS = 15 V, ID = 13 A IS = 3 A, VGS = 0 V IS = 3 A, VGS = 0 V, TJ = 125°C Dynamicb Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = 3 A, di/dt = 100 A/μs VDD = 15 V, RL = 15 Ω ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω VDS = 15 V, VGS = 4.5 V, ID = 13 A 37 10 8.8 17 6 83 37 34 37 10 8.8 17 14 102 26 42 ns n C Notes a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2%. b. Guaranteed by...