SUR50N03-09P Datasheet | Vishay

SPICE Device Model SUR50N03-09P Vishay Siliconix N-Channel 30-V (D-S) MOSFET CHARACTERISTICS - N-Channel Vertical DMOS - Macro Model (Subcircuit Model) - Level 3 MOS - Apply for both Linear and Switching Application - Accurate over the - 55 to 125°C Temperature Range - Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a mercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72801 14-Jun-04 .vishay. SPICE Device Model SUR50N03-09P Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current b Symbol Test Conditions Simulated Data 1.5 575 0.0073 0.011 0.012 0.91 Measured Data Unit VGS(th) ID(on) VDS = VGS, ID = 250 µA VDS = 5 V, VGS = 10 V VGS = 10 V, ID = 20 A V A 0.0076 Ω 0.0115 1.2 V Drain-Source On-State Resistanceb r...