FEATURES
D D D D D D D Anti Latchup Capability Monolithic Design High Slew Rate Low Offset/Drift Voltage Low Gate Leakage: 5 pA Low Noise High CMRR: 100 dB BENEFITS D D D D D D D External Substrate Bias—Avoids Latchup Tight Differential Match vs. Current Improved Op Amp Speed, Settling Time Accuracy Minimum Input Error/Trimming Requirement Insignificant Signal Loss/Error Voltage High System Sensitivity Minimum Error with Large Input Signal APPLICATIONS
D Wideband Differential Amps D High-Speed, Temp-Compensated, Single-Ended Input Amps D High Speed Comparators D Impedance Converters DESCRIPTION
Pins 4 and 8 of the SST series and pin 4 on the U series part numbers enable the substrate to be connected to a positive, external bias (VDD) to avoid latchup. Narrow Body SOIC S1 D1 G1 SUBSTRATE 1 2 3 4 8 7 6 5 SUBSTRATE G2 D2 S2 D1 2 3 Top View Marking Codes: SST5198NL - 5198NL SST5199NL - 5199NL CASE, SUBSTRATE Top View U5196NL, U5198NL U5197NL, U5199NL G1 4 5 S2 6 D2 S1 1 7 G2 The U series in the hermetically-sealed TO-78 package is available with full military processing.
Vishay
