• Part: VSC6048
  • Manufacturer: Vitesse Semiconductor
  • Size: 204.97 KB
Download VSC6048 Datasheet PDF
VSC6048 page 2
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VSC6048 Key Features

  • 8 Fully Integrated Timing Generators for ATE

VSC6048 Description

Reference Clock Selection Clock multiplication of x8 or x16 may be selected via the FSEL pin, requiring a reference clock of 100 ±2.5MHz or 50 ±1.25MHz, respectively. For system applications with 800MHz on board clock, the CMU can be bypassed by asserting BYP signal and RCK will accept an external 800MHz clock. In Bypass mode (BYP = 1, RCK = 800MHz) the skew from INX to RCK at the pin is 550ps +/-250ps.