VA2223 Overview
SD_B MUTE Swing Reference TTL Buffer TTL Buffer LINP Gain Adjust LINN Gain Adjust AGND VREG Power Limit Gate Driver PWM Logic VREG Gate Driver Ramp Generator Biases & References Startup Protection Logic SC Detect Thermal Protect DC Detect UVLO/OCLO VREG Power Limit Gate Driver PWM Logic VREG Gate Driver BSPR PVDDR ROUTP PVSS BSNR PVDDR ROUTN PVSS BSPL PVDDL LOUTP PVSS BSNL PVDDL LOUTN PVSS VA2223 Rev P.01 2 http://.viva-elec..tw Preliminary VA2223 Pin Assignments And Descriptions MODESEL SD_B RINP RINN PLIMIT VREG
VA2223 Key Features
- Operation Voltage from 4.5V to 26V
- Maximum 90% Efficiency with an 8Ω Speaker
- 2x30W@8Ω, THD+N <2% at 24V
- 2x30W@4Ω, THD+N =1% at 18V
- 1x50W@4Ω, THD+N=10% at 18V (PBTL)
- 1x60W@3Ω, THD+N<1% at 21V (PBTL)
- Multiple Switching Frequencies for AM Avoid
- Optional Clock Master/Slave Synchronization
- 4 Segments Configurable PWM Frequency
- Voltage-Divider Selectable Gain Settings