WDC W65C51S
the W65C51S operating modes and data checking parameters and determine operational status. The Command Register controls parity, receiver echo mode, transmitter interrupt control, the state of the RTSB line, receiver interrupt control and the state of the DTRB line. The Control Register controls the number of stop bits, word length, receiver clock source and baud rate.
| Part No. |
W65C51S |
| Datasheet |
W65C51S
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| Manufacturer |
 WDC |
| Description |
Asynchronous Communications Interface Adapter |
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DESCRIPTION
The WDC CMOS W65C51S Asynchronous Communications Interface Adapter (ACIA) provides an easily implemented, program controlled interface between 8-bit microprocessor based systems and serial communication data sets and modems. The ACIA has an internal baud rate generator. This feature eliminates the need for multiple component support circuits, a crystal being the only other part required. The Transmitter baud rate can be selected under program control to be either 1 of 15 different rates from 50 to 19,200 baud, or at 1/16 times an external clock rate. The Receiver baud rate may be selected under program control to be either the Transmitter rate or at 1/16 times the external clock rate. The ACIA has programmable word lengths of 5, 6, 7 or 8 bits; even, odd or no parity; 1, 1½ or 2 bit stops. The ACIA is designed for maximum-programmed control from the microprocessor (MPU) to simplify hardware implementation. Three separate registers permit the MPU to easily select The Status...
