FR1502 Datasheet | Western Digital

c o R p o R A T / o N a Yr. k .t - g'R" ! --.- '-1- - "PM' AM S + - Features GENERAL DESCRIPTION <e Xnl o 40 CHARACTERS BY 9 BITS o EXPANDABLE CHARACTER AND BIT SIZE (CASCADE CAPABILITY) o DC TO 1 MHz ASYNCHRONOUS 1/0 ACCESS >The FIFO (First-ln/First-Out) Storage Chip is an asynchron- ous memory organized in a nine-bit by forty-character stack. ~ Chara~ters are loaded at the top of the stack and then - 'sink" ~ to the bottom of the stack, or to the level of previously en- m tered data, without external clocks being applied. As a char- ~ o INPUTIOUTPUT READY STATUS FLAGS o THREE STATE OUTPUTS acter is taken from the bottom of the stack, all of the previollsly loaded characters will automatically propagate toward the output (bottom of stack). o SEPARATE INPUT AND OUTPUT ENABLES o DIRECTLY TTL PATIBLE o MASTER RESET o NO EXTERNAL CLOCKS REQUIRED o 28-PIN DIP PLASTIC OR CERAMIC PACKAGE Data can be entered whenever the INPUT REGISTER EMPTY line is high by strobing INPUT STROBE. The INPUT ENABLE line must also be high while strobing. The INPUT STROBE resets INPUT REGISTER EMPTY and latches the input data. As soon as this data is latched, INPUT REGISTER EMPTY will again go high and additional data can be loaded. APPLICATIONS POINT OF SALE TERMINALS DATA TRANSMISSION BUFFER LINE PRINTER INPUT BUFFER KEY-TO-TAPEIKEY-TO-DISC EQU IPMENT CARD/TAPE READERS AUTO DIALERS When data reaches the FIFO output, the OUTPUT DATA READY line will go high. The data is then valid at the outputs (providing the OUTPUT ENABLE line is high). The falling edge of the OUTPUT STROBE causes the OUTPUT DATA READY line to go low and to shift new data into the output register. When the new data is available, the OUTPUT DATA READY signal again goes high. The FIFO output data lines are in high impedance state whenever the OUTPUT ENABLE line is low. CRT BUFFER MEMORY CONTROL STACK SILO ORIENTED MACHINES PUTERITERMINALS 1/0 INTERFACE BUFFER The logic conventions and internal delays...