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WED3C755E8M-XBX - RISC MICROPROCESSOR MULTI-CHIP PACKAGE

Key Features

  • doze, nap, sleep and dynamic power management. The WED3C755E8M-XBX multichip package consists of: 755 RISC processor (E die revision) Dedicated 1MB SSRAM L2 cache, configured as 128Kx72 21mmx25mm, 255 Ceramic Ball Grid Array (CBGA) Core Frequency/L2 Cache Frequency (300MHz/ 150MHz, 350MHz/175MHz) Maximum 60x Bus frequency = 66MHz.

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Datasheet Details

Part number WED3C755E8M-XBX
Manufacturer White Electronic Designs Corporation
File Size 377.53 KB
Description RISC MICROPROCESSOR MULTI-CHIP PACKAGE
Datasheet download datasheet WED3C755E8M-XBX Datasheet

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The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com White Electronic Designs WED3C755E8M-XBX RISC MICROPROCESSOR MULTI-CHIP PACKAGE OVERVIEW The WEDC 755E/SSRAM multichip package is targeted for high performance, space sensitive, low power systems and supports the following power management features: doze, nap, sleep and dynamic power management.