W3H32M72E-XSBX - 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package

Description

Symbol ODT Type Input Description W3H32M72E-XSBX PRELIMINARY

On-Die termination: ODT (registered HIGH) enables termination resistance internal to the DDR2 SDRAM.

DQ71, LDM, UDM, LDQS, LDQS#, UDQS, and UDQS#.

Features

Data rate = 667.
, 533, 400 Package:.
208 Plastic Ball Grid Array (PBGA), 18 x 20mm.
1.0mm pitch Differential data strobe (DQS, DQS#) per byte www. DataSheet4U. com Internal, pipelined, double data rate architecture 4-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Four internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes On Die Termination (ODT) Adjustable da.

White Electronic Designs

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Datasheet Details

Part number	W3H32M72E-XSBX
Manufacturer	White Electronic Designs
File Size	965.20 KB
Description	32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package
Datasheet	W3H32M72E-XSBX Datasheet
Additional preview pages of the W3H32M72E-XSBX datasheet.

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Full PDF Text Transcription

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White Electronic Designs W3H32M72E-XSBX PRELIMINARY* 32M x 72 DDR2 SDRAM 208 PBGA Multi-Chip Package FEATURES Data rate = 667*, 533, 400 Package: • 208 Plastic Ball Grid Array (PBGA), 18 x 20mm • 1.0mm pitch Differential data strobe (DQS, DQS#) per byte www.DataSheet4U.com Internal, pipelined, double data rate architecture 4-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Four internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes On Die Termination (ODT) Adjustable data – output drive strength Single 1.8V ±0.

Published: May 14, 2010 |