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W78M64V-XSBX - Mx64 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip

Description

DQ0-63 A0-22 WE#1-4 CS#1-4 OE# RESET# WP#/ACC RY/BY# VCC VIO GND DNU Data Inputs/Outputs Address Inputs Write Enables Chip Selects Output Enable Hardware Reset Hardware Write Protection/Acceleration Ready/Busy Output Power Supply I/O Power Supply Ground Do Not Use GND DQ41 WE3# VIO DQ57 DNU W

Features

  • Access Times of 70, 90, 100, 120ns Packaging.
  • 159 PBGA, 13x22mm.
  • 1.27mm pitch 1,000,000 Erase/Program Cycles per sector Page Mode.
  • Page size is 8 words: Fast page read access from random locations within the page. Sector Architecture.
  • Bank A (16Mb): 4Kw x 8 and 32 Kw x 31.
  • Bank B (48Mb): 32Kw x 96.
  • Bank C (48Mb): 32Kw x 96.
  • Bank D (16Mb): 4Kw x 8 and 3Kw x 31 Both top and bottom boot blocks Zero Power Operation Organized as 8Mx64, us.

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Datasheet Details

Part number W78M64V-XSBX
Manufacturer White Electronic Designs
File Size 1.33 MB
Description Mx64 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip
Datasheet download datasheet W78M64V-XSBX Datasheet
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White Electronic Designs W78M64V-XSBX www.DataSheet4U.com 8Mx64 Flash 3.3V Page Mode Simultaneous Read/Write Operation Multi-Chip Package FEATURES Access Times of 70, 90, 100, 120ns Packaging • 159 PBGA, 13x22mm – 1.27mm pitch 1,000,000 Erase/Program Cycles per sector Page Mode • Page size is 8 words: Fast page read access from random locations within the page. Sector Architecture • Bank A (16Mb): 4Kw x 8 and 32 Kw x 31 • Bank B (48Mb): 32Kw x 96 • Bank C (48Mb): 32Kw x 96 • Bank D (16Mb): 4Kw x 8 and 3Kw x 31 Both top and bottom boot blocks Zero Power Operation Organized as 8Mx64, user configurable as 2x8Mx32 or 4x8Mx16 Commercial, Industrial and Military Temperature Ranges 3.
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