W3EG264M72AFSRXXXD3 Datasheet | White Electronic

FEATURES Double-data-rate architecture DDR200, DDR266 and DDR333: - JEDEC design specifications Phase-lock loop (PLL) clock driver to reduce loading Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank .. DESCRIPTION The W3EG264M72AFSR is a 2x64Mx72 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM ponents. The module consists of thirtysix 64Mx4, in FBGA packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. - This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. Power supply: VCC 2.5V ± 0.2V JEDEC standard 184 pin DIMM package - Package height option: Low-profile: 30.48mm (1.20") - Consult factory for availability of lead-free products. NOTE: Consult factory for availability of: - Ro HS pliant products - Vendor source control options - Industrial temperature option OPERATING FREQUENCIES DDR333 @CL=2.5 Clock Speed CL-t RCD-t RP 166MHz 2.5-3-3 DDR266 @CL=2 133MHz 2-2-2 DDR266 @CL=2 133MHz 2-3-3 DDR266 @CL=2.5 133MHz 2.5-3-3 DDR200 @CL=2 100MHz 2-2-2 November 2004 Rev. 1 White Electronic Designs Corporation - (602) 437-1520 - .wedc. White Electronic Designs PIN CONFIGURATION PIN# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 SYMBOL VREF DQ0 VSS DQ1 DQS0 DQ2 VCC DQ3 NC RESET# VSS DQ8 DQ9 DQS1 VCCQ NC NC VSS DQ10 DQ11 CKE0 VCCQ DQ16 DQ17 DQS2 VSS A9 DQ18 A7 VCCQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VCC DQ26 DQ27 A2 VSS...