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W3EG64128S-BD4 - 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED

Download the W3EG64128S-BD4 datasheet PDF. This datasheet also covers the W3EG64128S-AD4 variant, as both devices belong to the same 1gb - 2x64mx64 ddr sdram unbuffered family and are provided as variant models within a single manufacturer datasheet.

General Description

The W3EG64128S is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component.

The module consists of eight 128Mx8 stack DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock.

Key Features

  • Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V ± 0.2V JEDEC standard 200 pin SO-DIMM package.
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📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (W3EG64128S-AD4_WhiteElectronic.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number W3EG64128S-BD4
Manufacturer White Electronic
File Size 163.26 KB
Description 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED
Datasheet download datasheet W3EG64128S-BD4 Datasheet

More Datasheets from White Electronic

Part Number Description
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W3EG64128S-JD3 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED
W3EG6418S-D3 16Mx64 DDR SDRAM UNBUFFERED
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W3EG6432S-D4 32Mx64 DDR SDRAM UNBUFFERED
W3EG6432S-JD3 32Mx64 DDR SDRAM UNBUFFERED
W3EG6433S-AD4 256MB - 32Mx64 DDR SDRAM UNBUFFERED

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
White Electronic Designs W3EG64128S-AD4 -BD4 PRELIMINARY* 1GB – 2x64Mx64 DDR SDRAM UNBUFFERED w/PLL FEATURES Double-data-rate architecture Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank Power supply: 2.5V ± 0.2V JEDEC standard 200 pin SO-DIMM package • www.DataSheet4U.com DESCRIPTION The W3EG64128S is a 2x64Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of eight 128Mx8 stack DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate.