W3EG64255S-JD3 Datasheet PDF (2GB - 2x128Mx64 DDR SDRAM REGISTERED)

W3EG64255S-JD3 - 2GB - 2x128Mx64 DDR SDRAM REGISTERED

Description

The W3EG64255S is a 2x128Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component.

The module consists of sixteen 256Mx4 stacks, in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock.

Features

Double-data-rate architecture DDR200, DDR266 and DDR333;.
JEDEC design speciﬁcations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: VCC 2.5V ± 0.2V www. DataSheet4U. com.

Datasheet Details

Part number	W3EG64255S-JD3
Manufacturer	White Electronic
File Size	229.40 KB
Description	2GB - 2x128Mx64 DDR SDRAM REGISTERED
Datasheet	W3EG64255S-JD3 Datasheet
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White Electronic Designs W3EG64255S-JD3 ADVANCED* 2GB – 2x128Mx64 DDR SDRAM REGISTERED, w/PLL FEATURES Double-data-rate architecture DDR200, DDR266 and DDR333; • JEDEC design speciﬁcations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Dual Rank Power supply: VCC 2.5V ± 0.2V www.DataSheet4U.com DESCRIPTION The W3EG64255S is a 2x128Mx64 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM component. The module consists of sixteen 256Mx4 stacks, in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Published: Jun 8, 2007 |

Datasheet Details

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