W3EG64255S-JD3 Key Features
- JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Late
| Part Number | Description |
|---|---|
| W3EG64128S-AD4 | 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED |
| W3EG64128S-BD4 | 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED |
| W3EG64128S-D3 | 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED |
| W3EG64128S-JD3 | 1GB - 2x64Mx64 DDR SDRAM UNBUFFERED |
| W3EG6418S-D3 | 16Mx64 DDR SDRAM UNBUFFERED |