W3EG7232S-AD4 Key Features
- JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Late
| Part Number | Description |
|---|---|
| W3EG7232S-BD4 | 256MB - 32Mx72 DDR SDRAM UNBUFFERED |
| W3EG7234S-AJD3 | 256MB - 32Mx72 DDR SDRAM REGISTERED |
| W3EG7234S-D3 | 256MB - 32Mx72 DDR SDRAM REGISTERED |
| W3EG7234S-JD3 | 256MB - 32Mx72 DDR SDRAM REGISTERED |
| W3EG7235S-JD3 | 256MB - 2x16Mx72 DDR SDRAM REGISTERED ECC |