W3EG7264S-D3 - 512MB - 64Mx72 DDR SDRAM UNBUFFERED

Description

The W3EG7264S is a 64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components.

The module consists of nine 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 184 pin FR4 substrate.

Synchronous design allows precise cycle control with the use of system clock.

Features

Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400.
JEDEC design speciﬁcations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply: DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V www. DataSheet.

White Electronic

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Datasheet Details

Part number	W3EG7264S-D3
Manufacturer	White Electronic
File Size	199.36 KB
Description	512MB - 64Mx72 DDR SDRAM UNBUFFERED
Datasheet	W3EG7264S-D3 Datasheet
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White Electronic Designs W3EG7264S-JD3-D3 PRELIMINARY* 512MB – 64Mx72 DDR SDRAM UNBUFFERED FEATURES Double-data-rate architecture DDR200, DDR266, DDR333 and DDR400 • JEDEC design speciﬁcations Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input. Auto and self refresh Serial presence detect Power supply: DDR333, 266, 200: VCC = VCCQ = +2.5V ± 0.2V; DDR400: VCC = VCCQ = +2.6V ± 0.1V www.DataSheet4U.com DESCRIPTION The W3EG7264S is a 64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components.

Published: Jun 8, 2007 |