Description
The WED2EG472512V is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x512Kx72.
Features
- 4x512Kx72 Synchronous Burst Pipeline Architecture; Dual Cycle Deselect Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1#-BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Asynchronous Output Enable (G#) Internally Self-Timed Write Individual Bank Sleep Mode Enabl.