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WED2EG472512V-D2 - DUAL KEY DIMM

General Description

The WED2EG472512V is a Synchronous/Synchronous Burst SRAM, 84 position Dual Key; Double High DIMM (168 contacts) Module, organized as 4x512Kx72.

Key Features

  • 4x512Kx72 Synchronous Burst Pipeline Architecture; Dual Cycle Deselect Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1#-BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Asynchronous Output Enable (G#) Internally Self-Timed Write Individual Bank Sleep Mode Enabl.

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Datasheet Details

Part number WED2EG472512V-D2
Manufacturer White Electronic
File Size 291.66 KB
Description DUAL KEY DIMM
Datasheet download datasheet WED2EG472512V-D2 Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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www.DataSheet4U.com White Electronic Designs WED2EG472512V-D2 ADVANCED* 16MB (4x512Kx72) SYNC BURST PIPELINE, DUAL KEY DIMM FEATURES 4x512Kx72 Synchronous Burst Pipeline Architecture; Dual Cycle Deselect Linear and Sequential Burst Support via MODE pin Clock Controlled Registered Module Enable (EM#) Clock Controlled Registered Bank Enables (E1#, E2#, E3#, E4#) Clock Controlled Byte Write Mode Enable (BWE#) Clock Controlled Byte Write Enables (BW1#-BW8#) Clock Controlled Registered Address Clock Controlled Registered Global Write (GW#) Asynchronous Output Enable (G#) Internally Self-Timed Write Individual Bank Sleep Mode Enables (ZZ1, ZZ2, ZZ3, ZZ4) Gold Lead Finish 3.3V ± 10% Operation Frequency(s): 200, 166, 150 and 133MHZ Access Apeed(s): tKHQV = 3.0, 3.5, 3.7 and 4.