Winbond Electronics Corporation W25S243A
The W25S243A is a high-speed, low-power, synchronous-burst pipelined, CMOS static RAM organized as 65,536 × 64 bits that operates on a single 3.3-volt power supply. The mode to be executed is controlled by the LBO pin. VDDQ VSSQ VDD VSS RSV NC I/O power supply I/O ground Power supply Ground Reserved pin, don't use these pins No connection DESCRIPTION -3- Publication Release Date: November 1998 Revision A1 Preliminary W25S243A FUNCTIONAL DESCRIPTION The W25S243A is a synchronous-burst pipelined SRAM designed for...| Part No. | W25S243A |
|---|---|
| Datasheet | W25S243A Download |
| Manufacturer |  Winbond Electronics Corporation |
| Description | 64K X 64 BURST PIPELINED HIGH-SPEED CMOS STATIC RAM |
| Buy | Stock & Price |
GENERAL DESCRIPTION
A built-in two-bit burst address counter supports both Pentium™ burst mode and linear burst mode. Pipelining or non-pipelining of the data outputs is controlled by the FT pin. A snooze mode can reduces power dissipation. This device supports 3-1-1-1-2-1-1-1 in a two-bank, back-to-back burst read cycle.FEATURES
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● Synchronous operation High-speed access time: 12 nS Single +3.3V power supply Individual byte write capability 3.3V LVTTL compatible I/O Clock-controlled and registered input Asynchronous output enable
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● Pipelined/non-pipelined data output capability Supports snooze mode (low-power state) Internal burst counter supports Intel burst (Interleaved) mode & linear burst mode Supports 2T/1T mode Packaged in 128-pin QFP and TQFP BLOCK DIAGRAM A(15:0) INPUT REGISTER 64K X 64 CORE ARRAY CLK CE(3:1) GW BWE BW(8:1) OE ADSC ADSP ADV LBO FT ZZ CONTROL LOGIC REGISTER DATA I/O REGISTER I/O(64:1) -1- Publication Release Date: November 1998 Revision A1 P...
