W6691
Description
W6691 consists of one D channel HDLC controller and two B HDLC controller channel access.
Key Features
- Full Duplex 2B+D S/T interface transceiver pliant with ITU I.430 Remendation
- One D channel HDLC controller
- Maskable address recognition - Transparent (HDLC) mode - FIFO buffer (2 * 64)
- Two B channel HDLC controller - Maskable address recognition - Transparent (HDLC) mode - FIFO buffer (2 * 128)
- Various B channel switching capabilities and PCM inter
- Two PCM CODEC interfaces for speech and POTS application
- GCI interface connects with other peripheral device in TE, LT-S and LT-T mode
- Multi-frame synchronization
- 8-bits Intel mode or Motorola mode interface accesses B channel and mand/Indication channel
- The timing clock recovery depends on operating mode
