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W83178S Datasheet 100 Mhz 3-dimm Sdram Buffer

Manufacturer: Winbond

Overview: W83178S 100MHZ 3-DIMM SDRAM BUFFER W83178S Data Sheet Revision History Pages 1 2 3 4 5 6 7 8 9 10 n.a. n.a. 02/Apr 1.0 Dates Version Version On Web n.a. 1.0 All of the versions before 0.50 are for internal use. Change version and version on web site to 1.0 Main Contents Please note that all data and specifications are subject to change without notice. All the trademarks of products and panies mentioned in this data sheet belong to their respective owners. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. -1- Publication Release Date: Sep. 1998 Revision 1.0 W83178S 1.

Datasheet Details

Part number W83178S
Manufacturer Winbond
File Size 429.42 KB
Description 100 MHZ 3-DIMM SDRAM BUFFER
Datasheet W83178S_Winbond.pdf

General Description

The W83178S is a 13 outputs SDRAM clock buffer for 3-DIMMs models incorporate with W83196S-14 which is the clock synthesizer especially for the 100MHz models such as Intel BX chipsets.(Refer the datasheet fo Winbond W83196S-14) The W83178S receives the clock from chipset by the Buffer_In pin and provides almost zero-delay (less than 4ns propagation delay) SDRAM buffer outputs for the 13 SDRAM clocks which are synchronous with the CPU clock outputs priovided by W83196S-14.

The clock skew between any two clock outputs is less than 250ps and the output buffer impedance is about 15 ohms.

The W83178S also provides I2C serial bus interface to program the registers to enable or disable each SDRAM clock outputs.

Key Features

  • Supports Intel Pentium II CPUs for BX chipset.
  • 13 SDRAM clocks for 3-DIMMs.
  • Clock skew less than 250ps.
  • Almost none delay Buffer-in controlling SDRAM clocks(< 4ns propagation delay).
  • I2C 2-wire serial interface.
  • Programmable registers to enable/stop each output.
  • Incorporate with W83196S-14.
  • 28pin-SOP package -2- Publication Release Date: Sep. 1998 Revision 1.0 W83178S 3.0 BLOCK.

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W83178S Distributor