W83193R-01 Datasheet | Winbond

DESCRIPTION The W83193R-01 is a Clock Synthesizer which provides all clocks required for high-speed RISC or CISC microprocessor such as Intel Pentium Pro , AMD or Cyrix. Eight different frequency of CPU and PCI clocks are externally selectable with smooth transitions. The W83193R-02/-04 also provides I2C serial bus interface to program the registers to enable or disable each clock outputs and choose the 0.6% or 1.5% center type spread spectrum. The W83193R-01 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI and SDRAM CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 p F loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 p F loads as maintaining 50¡Ó 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES - - - - - - - - - - - - - - - - Supports Pentium™, Pentium™ Pro, Pentium™ II, AMD and Cyrix CPUs with I2C. 4 CPU clocks. 12 SDRAM clocks for 3 DIMs. 7 PCI synchronous clocks. One IOAPIC clock for multiprocessor support. Optional single or mixed supply: (Vdd = Vddq3 = Vddq2 = 3.3V) or (Vdd = Vddq3 = 3.3V, Vddq2 = 2.5V) < 250ps skew among CPU and SDRAM clocks. < 250ps skew among PCI clocks. Smooth frequency switch with selections from 50 MHz to 83.3 MHz CPU. I2C 2-Wire serial interface. 0.6% or 1.5% center type spread spectrum function to reduce EMI. Programmable registers to enable/stop each output and select modes. (mode as Tri-state, or Normal ) MODE pin for power Management. 48 MHz for USB. 24 MHz for super I/O. 48-pin SSOP package. Publication Release Date: May 1998 Revision 0.20 -1- PRELIMINARY 3.0 BLOCK DIAGRAM Vdd Xin Xout - SDATA - SDCLK REF OSC Vddq2 b CPU_stop# Vddq2 Stop clock Vddq3 PLL 1 SDRAM[0:11] Buffers PCI_stop# Stop - MODE - CPU3.3#_2.5 - FS[0:2] - CPU_STOP# - PCI_STOP # clock LATC H Contr ol Logic PLL2 Vddq3 Dela y Vddq3 Buffers PCICLK_F PCICLK[0:5] Buffers Buffers...