W83194BR-97 Datasheet | Winbond

DESCRIPTION The W83194BR-97 is a Clock Synthesizer for Intel Camino 820 chipset. W83194BR-97 provides all clocks required for high-speed RISC or CISC microprocessor and also provides 64 sets of different frequencies of CPU, PCI, 3V66, IOAPIC clocks or stepless frequecies programming by M/N value via 2 I C registers. All clocks are externally selectable with smooth transitions. The W83194BR-97 provides I C serial bus interface to program the registers to enable or disable each clock outputs and provides 0.5% and 0.25% center type spread spectrum to reduce EMI. The W83194BR-97 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1 V /ns slew rate into 30 p F loads. CPU CLOCK outputs typically provide better than 1 V /ns slew rate into 20 p F loads as maintaining 50± 5% duty cycle. The fixed frequency outputs as REF, 24MHz, and 48 MHz provide better than 0.5V /ns slew rate. 2.0 PRODUCT FEATURES - - - - - - - - - - - - - - - - - 2 CPU clock outputs One CPU/2 output as reference input to DRCG 3 3V66 clock outputs 3 IOAPIC clock outputs 8 PCI synchronous clocks. Optional single or mixed supply: (Vdd Q2 = Vdd Q3 = 3.3V or Vdd Q3=3.3V, Vdd Q2=2.5V) CPU to 3V66 offset 0 to 1.5 ns 3V66 to PCI offset 1.5 to 4.0 ns Skew form CPU to PCI clock 1 to 4 ns, center 2.6 ns Smooth frequency switch with selections from 66.8 to 200MHz 2 Stepless programmable frequencies by I C register9 ~ register12 2 2 I C 2-Wire serial interface and I C read back 0.5% and 0.75% center type spread spectrum Programmable registers to enable/stop each output and select modes (mode as Tri-state or Normal ) 48 MHz pins for USB 24 MHz for super I/O 48-pin SSOP package -1- Publication Release Date: Dec. 1999 Revision 0.35 PRELIMINARY 3.0 PIN CONFIGURATION VSSR REF0 REF1/- SEL24_48# VDDR Xin Xout VSSP PCICLK_F/ - FS0 PCICLK1/ - FS1 VDDP PCICLK2/ - FS2 PCICLK3/ - FS3 VSSPCI PCICLK4 PCICLK5 VDDP PCICLK6 PCICLK7 VSSPCI...