GENERAL DESCRIPTION
W89C841F supports full/half duplex, asymmetrical flow control operation compliant with IEEE 802.3x and VLAN tagged frame compliant with IEEE 802.1p. According to different applications, W89C841F can be configured into one of 3 modes to operate by setting the pins CONFIG[1:0] and ModeSel[2:0] after power-on reset. The 3 operational modes of W89C841F are listed as below. 1. PCI Ethernet MAC controller with internal Ethernet PHYceiver. 2. Pure PCI Ethernet MAC Controller 3. Pure 10/100M PHYceiver W89C841F provides a host bus interface complying with the PCI local bus specification R2.2, Mini PCI Specification R1.0 and CardBus. W89C841F plays as a bus master role to improve network performance and reduce the bus utilization. There are built-in 2K bytes TX FIFO and 2K bytes RX FIFO to store data. The DMA controller handles the data transfer between the host memory and the FIFOs. The data received from network are queued into the RX FIFO then directly moved into the host memory through the PCI bus.